1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2016 by Adrian Wise. 5// SPDX-License-Identifier: CC0-1.0 6 7//bug1104 8 9module t (input clk); 10 simple_bus sb_intf(clk); 11 simple_bus #(.DWIDTH(16)) wide_intf(clk); 12 mem mem(sb_intf.slave); 13 cpu cpu(sb_intf.master); 14 mem memW(wide_intf.slave); 15 cpu cpuW(wide_intf.master); 16endmodule 17 18interface simple_bus #(AWIDTH = 8, DWIDTH = 8) 19 (input logic clk); // Define the interface 20 21 logic req, gnt; 22 logic [AWIDTH-1:0] addr; 23 logic [DWIDTH-1:0] data; 24 25 modport slave( input req, addr, clk, 26 output gnt, 27 input data); 28 29 modport master(input gnt, clk, 30 output req, addr, 31 output data); 32 33 initial begin 34 if (DWIDTH != 16) $stop; 35 end 36endinterface: simple_bus 37 38module mem(interface a); 39 logic avail; 40 always @(posedge a.clk) 41 a.gnt <= a.req & avail; 42 initial begin 43 if ($bits(a.data) != 16) $stop; 44 $write("*-* All Finished *-*\n"); 45 $finish; 46 end 47endmodule 48 49module cpu(interface b); 50endmodule 51