1// DESCRIPTION: Verilator: Verilog Test module 2// 3// A test of the +verilog2001ext+ and +verilog2005ext+ flags. 4// 5// This file ONLY is placed under the Creative Commons Public Domain, for 6// any use, without warranty, 2019 by Wilson Snyder. 7// SPDX-License-Identifier: CC0-1.0 8 9// verilator lint_off SYMRSVDWORD 10 11module t(input do); 12 t_langext_order_sub sub (.do(do)); 13endmodule 14