1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2021 by Donald Owen.
5// SPDX-License-Identifier: CC0-1.0
6
7module t ();
8   if (1) begin: GenConstFunc
9      // IEEE 1800-2017 13.4.3, constant functions shall not be declared inside a
10      //generate block
11      function automatic bit constFunc();
12         constFunc = 1'b1;
13      endfunction
14
15      localparam PARAM = constFunc();
16    end
17endmodule
18