1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2017 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7interface dummy_if (); 8 logic signal; 9 10 modport slave 11 (output signal); 12 13 modport master 14 (input signal); 15endinterface: dummy_if 16 17module sub 18 ( 19 input wire signal_i, 20 output wire signal_o, 21 22 dummy_if.master dummy_in, 23 dummy_if.slave dummy_out 24 ); 25 26 assign dummy_in.signal = signal_i; 27 assign signal_o = dummy_out.signal; 28endmodule 29 30 31module t (/*AUTOARG*/ 32 // Outputs 33 signal_o, 34 // Inputs 35 signal_i 36 ); 37 input signal_i; 38 output signal_o; 39 40 dummy_if dummy_if (); 41 42 sub sub 43 ( 44 .signal_i(signal_i), 45 .signal_o(signal_o), 46 .dummy_in(dummy_if), 47 .dummy_out(dummy_if) 48 ); 49 50endmodule 51