1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7/* verilator lint_off PINNOTFOUND */
8module a;
9localparam A=1;
10generate
11if (A==0)
12begin
13b b_inst1 (.x(1'b0)); // nonexistent port
14b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter
15end
16endgenerate
17endmodule
18
19module b;
20endmodule
21