1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2017 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (input mispkg::foo_t a);
8 reg mispkgb::bar_t b;
9endmodule
10