1%Warning-WIDTH: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?sh10' generates 32 or 5 bits. 2 : ... In instance t 3 25 | rg = g; 4 | ^ 5 ... For warning description see https://verilator.org/warn/WIDTH?v=latest 6 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. 7%Warning-WIDTH: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. 8 : ... In instance t 9 26 | rp = P; 10 | ^ 11%Warning-WIDTH: t/t_lint_width_genfor_bad.v:27:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits. 12 : ... In instance t 13 27 | rw = w; 14 | ^ 15%Warning-WIDTH: t/t_lint_width_genfor_bad.v:28:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. 16 : ... In instance t 17 28 | rc = 64'h1; 18 | ^ 19%Warning-WIDTH: t/t_lint_width_genfor_bad.v:33:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. 20 : ... In instance t 21 33 | ri = i; 22 | ^ 23%Error: Exiting due to 24