1// DESCRIPTION: Verilator: Verilog Test module
2// This file ONLY is placed under the Creative Commons Public Domain, for
3// any use, without warranty, 2009 by Wilson Snyder.
4// SPDX-License-Identifier: CC0-1.0
5
6module t (/*AUTOARG*/
7   // Inputs
8   clk
9   );
10   input clk;
11
12   integer 	cyc = 0;
13   reg [63:0] 	crc;
14   reg [63:0] 	sum;
15
16   // Take CRC data and apply to testblock inputs
17   wire [15:0]  in = crc[15:0];
18
19   /*AUTOWIRE*/
20   // Beginning of automatic wires (for undeclared instantiated-module outputs)
21   wire [15:0]		outa;			// From test of Test.v
22   wire [15:0]		outb;			// From test of Test.v
23   wire [15:0]		outc;			// From test of Test.v
24   // End of automatics
25
26   Test test (/*AUTOINST*/
27	      // Outputs
28	      .outa			(outa[15:0]),
29	      .outb			(outb[15:0]),
30	      .outc			(outc[15:0]),
31	      // Inputs
32	      .clk			(clk),
33	      .in			(in[15:0]));
34
35   // Aggregate outputs into a single result vector
36   wire [63:0] result = {16'h0, outa, outb, outc};
37
38   // Test loop
39   always @ (posedge clk) begin
40`ifdef TEST_VERBOSE
41      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
42`endif
43      cyc <= cyc + 1;
44      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
45      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
46      if (cyc==0) begin
47	 // Setup
48	 crc <= 64'h5aef0c8d_d70a4497;
49	 sum <= 64'h0;
50      end
51      else if (cyc<10) begin
52	 sum <= 64'h0;
53      end
54      else if (cyc<90) begin
55      end
56      else if (cyc==99) begin
57	 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
58	 if (crc !== 64'hc77bb9b3784ea091) $stop;
59	 // What checksum will we end up with (above print should match)
60`define EXPECTED_SUM 64'h09be74b1b0f8c35d
61	 if (sum !== `EXPECTED_SUM) $stop;
62	 $write("*-* All Finished *-*\n");
63	 $finish;
64      end
65   end
66
67endmodule
68
69module Test (/*AUTOARG*/
70   // Outputs
71   outa, outb, outc,
72   // Inputs
73   clk, in
74   );
75
76   input clk;
77   input [15:0]      in;
78   output reg [15:0] outa;
79   output reg [15:0] outb;
80   output reg [15:0] outc;
81
82   parameter WIDTH = 0;
83   always @(posedge clk) begin
84      outa <= {in};
85      outb <= {{WIDTH{1'b0}}, in};
86      outc <= {in, {WIDTH{1'b0}}};
87   end
88endmodule
89