1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2019 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 integer cyc = 0; 14 reg [63:0] crc; 15 reg [63:0] sum; 16 17 // Take CRC data and apply to testblock inputs 18 wire [3:0] cnt = crc[3:0]; 19 wire [6:0] decr = crc[14:8]; 20 21 /*AUTOWIRE*/ 22 // Beginning of automatic wires (for undeclared instantiated-module outputs) 23 wire [3:0] next; // From test of Test.v 24 // End of automatics 25 26 Test test (/*AUTOINST*/ 27 // Outputs 28 .next (next[3:0]), 29 // Inputs 30 .cnt (cnt[3:0]), 31 .decr (decr[6:0])); 32 33 // Aggregate outputs into a single result vector 34 wire [63:0] result = {60'h0, next}; 35 36 // Test loop 37 always @ (posedge clk) begin 38`ifdef TEST_VERBOSE 39 $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); 40`endif 41 cyc <= cyc + 1; 42 crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; 43 sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; 44 if (cyc==0) begin 45 // Setup 46 crc <= 64'h5aef0c8d_d70a4497; 47 sum <= '0; 48 end 49 else if (cyc<10) begin 50 sum <= '0; 51 end 52 else if (cyc<90) begin 53 end 54 else if (cyc==99) begin 55 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); 56 if (crc !== 64'hc77bb9b3784ea091) $stop; 57 // What checksum will we end up with (above print should match) 58`define EXPECTED_SUM 64'h7cd85c944415d2ef 59 if (sum !== `EXPECTED_SUM) $stop; 60 $write("*-* All Finished *-*\n"); 61 $finish; 62 end 63 end 64 65endmodule 66 67module Test (/*AUTOARG*/ 68 // Outputs 69 next, 70 // Inputs 71 cnt, decr 72 ); 73 74 input [3:0] cnt; 75 input signed [6:0] decr; 76 output reg [3:0] next; 77 78 always_comb begin 79 reg signed [6:0] tmp; 80 tmp = 0; 81 // verilator lint_off WIDTH 82 tmp = ($signed({1'b0, cnt}) - decr); 83 // verilator lint_on WIDTH 84 if ((tmp > 15)) begin 85 next = 15; 86 end 87 else if ((tmp < 0)) begin 88 next = 0; 89 end 90 else begin 91 next = tmp[3:0]; 92 end 93 end 94 95endmodule 96