1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2014 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13
14   integer 	cyc = 0;
15   reg [63:0] 	crc;
16   reg [63:0] 	sum;
17
18   //bug765; disappears if add this wire
19   //wire [7:0]  a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]);  // favor low values
20   wire [7:0]  a = crc[7:0];
21
22   /*AUTOWIRE*/
23   // Beginning of automatic wires (for undeclared instantiated-module outputs)
24   wire [15:0]		y;			// From test of Test.v
25   // End of automatics
26
27   Test test (/*AUTOINST*/
28	      // Outputs
29	      .y			(y[15:0]),
30	      // Inputs
31	      .a			(a[7:0]));
32
33   // Aggregate outputs into a single result vector
34   wire [63:0] result = {48'h0, y};
35
36   // Test loop
37   always @ (posedge clk) begin
38`ifdef TEST_VERBOSE
39      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
40`endif
41      cyc <= cyc + 1;
42      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
43      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
44      if (cyc==0) begin
45	 // Setup
46	 crc <= 64'h5aef0c8d_d70a4497;
47	 sum <= 64'h0;
48      end
49      else if (cyc<10) begin
50	 sum <= 64'h0;
51      end
52      else if (cyc<90) begin
53      end
54      else if (cyc==99) begin
55	 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
56	 if (crc !== 64'hc77bb9b3784ea091) $stop;
57	 // What checksum will we end up with (above print should match)
58`define EXPECTED_SUM 64'h0
59	 if (sum !== `EXPECTED_SUM) $stop;
60	 $write("*-* All Finished *-*\n");
61	 $finish;
62      end
63   end
64
65endmodule
66
67module Test (/*AUTOARG*/
68   // Outputs
69   y,
70   // Inputs
71   a
72   );
73   input signed [7:0] a;
74   output [15:0]      y;
75   // verilator lint_off WIDTH
76   assign y = ~66'd0 <<< {4{a}};
77   // verilator lint_on WIDTH
78endmodule
79