1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2006 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13
14   integer cyc; initial cyc=1;
15   always @ (posedge clk) begin
16      if (cyc!=0) begin
17	 cyc <= cyc + 1;
18	 if (cyc==1) begin
19	    // New number format
20	    if ('0 !== {66{1'b0}}) $stop;
21	    if ('1 !== {66{1'b1}}) $stop;
22	    if ('x !== {66{1'bx}}) $stop;
23	    if ('z !== {66{1'bz}}) $stop;
24`ifndef NC	// NC-Verilog 5.50-s09 chokes on this test
25	    if ("\v" != 8'd11) $stop;
26	    if ("\f" != 8'd12) $stop;
27	    if ("\a" != 8'd7) $stop;
28	    if ("\x9a" != 8'h9a) $stop;
29	    if ("\xf1" != 8'hf1) $stop;
30`endif
31	 end
32	 if (cyc==8) begin
33	 end
34	 if (cyc==9) begin
35	    $write("*-* All Finished *-*\n");
36	    $finish;
37	 end
38      end
39   end
40
41endmodule
42