1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2008 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11   input clk;
12
13   integer 	cyc = 0;
14   reg [63:0] 	crc;
15   reg [63:0] 	sum;
16
17   /*AUTOWIRE*/
18   // Beginning of automatic wires (for undeclared instantiated-module outputs)
19   wire [2:0]		q;			// From test of Test.v
20   // End of automatics
21
22   Test test (
23	      // Outputs
24	      .q			(q[2:0]),
25	      // Inputs
26	      .clk			(clk),
27	      .reset_l			(crc[0]),
28	      .enable			(crc[2]),
29	      .q_var0			(crc[19:10]),
30	      .q_var2			(crc[29:20]),
31	      .q_var4			(crc[39:30]),
32	      .q_var6			(crc[49:40])
33	      /*AUTOINST*/);
34
35   // Aggregate outputs into a single result vector
36   wire [63:0] result = {61'h0,q};
37
38   // Test loop
39   always @ (posedge clk) begin
40`ifdef TEST_VERBOSE
41      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
42`endif
43      cyc <= cyc + 1;
44      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
45      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
46      if (cyc==0) begin
47	 // Setup
48	 crc <= 64'h5aef0c8d_d70a4497;
49      end
50      else if (cyc<10) begin
51	 sum <= 64'h0;
52      end
53      else if (cyc<90) begin
54      end
55      else if (cyc==99) begin
56	 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
57	 if (crc !== 64'hc77bb9b3784ea091) $stop;
58`define EXPECTED_SUM 64'h58b162c58d6e35ba
59	 if (sum !== `EXPECTED_SUM) $stop;
60	 $write("*-* All Finished *-*\n");
61	 $finish;
62      end
63   end
64endmodule
65
66
67module Test
68  (
69   input               clk,
70   input               reset_l,
71   input               enable,
72
73   input       [ 9:0]  q_var0,
74   input       [ 9:0]  q_var2,
75   input       [ 9:0]  q_var4,
76   input       [ 9:0]  q_var6,
77
78   output reg  [2:0]   q
79   );
80
81   reg [7:0] 	       p1_r [6:0];
82
83   always @(posedge clk) begin
84      if (!reset_l) begin
85         p1_r[0]       <= 'b0;
86         p1_r[1]       <= 'b0;
87         p1_r[2]       <= 'b0;
88         p1_r[3]       <= 'b0;
89         p1_r[4]       <= 'b0;
90         p1_r[5]       <= 'b0;
91         p1_r[6]       <= 'b0;
92      end
93      else if (enable) begin : pass1
94         match(q_var0, q_var2, q_var4, q_var6);
95      end
96   end
97
98   // verilator lint_off WIDTH
99   always @(posedge clk) begin : l
100      reg [10:0]  bd;
101      reg [3:0]   idx;
102
103      q = 0;
104      bd = 0;
105      for (idx=0; idx<7; idx=idx+1) begin
106	 q       = idx+1;
107	 bd    = bd + p1_r[idx];
108      end
109   end
110
111
112   task match;
113      input   [9:0]   p0, p1, p2, p3;
114      reg [9:0]       p[3:0];
115      begin
116	 p[0]  = p0;
117	 p[1]  = p1;
118	 p[2]  = p2;
119	 p[3]  = p3;
120         p1_r[0] <= p[0];
121         p1_r[1] <= p[1];
122      end
123   endtask
124endmodule
125