1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This test verifies that a top-module can be specified which 4// is instantiated beneath another module in the compiled source 5// code. 6// 7// This file ONLY is placed under the Creative Commons Public Domain, for 8// any use, without warranty, 2021 by Dan Petrisko 9// SPDX-License-Identifier: CC0-1.0 10 11module top(/*AUTOARG*/ 12 // Inputs 13 clk 14 ); 15 input clk; 16 17 always_ff @(posedge clk) begin 18 $write("*-* All Finished *-*\n"); 19 $finish(); 20 end 21 22endmodule 23 24module faketop(/*AUTOARG*/ 25 ); 26 27 top top(); 28 29 // Stop immediately if this module is instantiated 30 initial begin 31 $stop(); 32 end 33 34endmodule 35