1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t(/*AUTOARG*/ 8 // Outputs 9 q0, q1, q2, q3, q4, 10 // Inputs 11 clk, rst, en, i0, i1, i2, i3, i4 12 ); 13 input clk; 14 15 input rst; 16 input en; 17 output int q0; input int i0; 18 output int q1; input int i1; 19 output int q2; input int i2; 20 output int q3; input int i3; 21 output int q4; input int i4; 22 23 always @ (posedge clk) begin 24 if (rst) begin 25 if (en) q0 <= i0; 26 end 27 else q0 <= 0; 28 29 if (rst) begin 30 if (en) q1 <= i1; 31 end 32 else q1 <= 0; 33 34 if (rst) begin 35 if (en) q2 <= i2; 36 end 37 else q2 <= 0; 38 39 if (rst) begin 40 if (en) q3 <= i3; 41 end 42 else q3 <= 0; 43 end 44 45 always_comb begin 46 q4 = i4; 47 if (q4 == 0) begin 48 // Conflicts with condition 49 q4 = 1; 50 end 51 if (q4 == 0) begin 52 // Conflicts with condition 53 q4 = 2; 54 end 55 end 56 57endmodule 58