1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2003 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   // surefire lint_off ASWEBB
13   // surefire lint_off ASWEMB
14   // surefire lint_off STMINI
15   // surefire lint_off CSEBEQ
16
17   input clk;
18
19   reg [7:0] a_to_clk_levm3;
20   reg [7:0] b_to_clk_levm1;
21   reg [7:0] c_com_levs10;
22   reg [7:0] d_to_clk_levm2;
23   /*AUTOWIRE*/
24   // Beginning of automatic wires (for undeclared instantiated-module outputs)
25   wire [7:0]		m_from_clk_lev1_r;	// From a of t_order_a.v
26   wire [7:0]		n_from_clk_lev2;	// From a of t_order_a.v
27   wire [7:0]		o_from_com_levs11;	// From a of t_order_a.v
28   wire [7:0]		o_from_comandclk_levs12;// From a of t_order_a.v
29   wire [7:0]		o_subfrom_clk_lev2;	// From b of t_order_b.v
30   // End of automatics
31
32   reg [7:0] cyc; initial cyc = 0;
33
34   t_order_a a (
35		.one			(8'h1),
36		/*AUTOINST*/
37		// Outputs
38		.m_from_clk_lev1_r	(m_from_clk_lev1_r[7:0]),
39		.n_from_clk_lev2	(n_from_clk_lev2[7:0]),
40		.o_from_com_levs11	(o_from_com_levs11[7:0]),
41		.o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]),
42		// Inputs
43		.clk			(clk),
44		.a_to_clk_levm3		(a_to_clk_levm3[7:0]),
45		.b_to_clk_levm1		(b_to_clk_levm1[7:0]),
46		.c_com_levs10		(c_com_levs10[7:0]),
47		.d_to_clk_levm2		(d_to_clk_levm2[7:0]));
48
49   t_order_b b (
50		/*AUTOINST*/
51		// Outputs
52		.o_subfrom_clk_lev2	(o_subfrom_clk_lev2[7:0]),
53		// Inputs
54		.m_from_clk_lev1_r	(m_from_clk_lev1_r[7:0]));
55
56   reg [7:0]  o_from_com_levs12;
57   reg [7:0]  o_from_com_levs13;
58   always @ (/*AS*/o_from_com_levs11) begin
59      o_from_com_levs12 = o_from_com_levs11 + 8'h1;
60      o_from_com_levs12 = o_from_com_levs12 + 8'h1;  // Test we can add to self and optimize
61      o_from_com_levs13 = o_from_com_levs12;
62   end
63
64   reg  	sepassign_in;
65   // verilator lint_off UNOPTFLAT
66   wire [3:0] 	sepassign;
67   // verilator lint_on UNOPTFLAT
68
69   // verilator lint_off UNOPT
70   assign #0.1	sepassign[0]	= 0,
71   	  	sepassign[1]	= sepassign[2],
72   	  	sepassign[2]	= sepassign[3],
73    	  	sepassign[3]	= sepassign_in;
74   wire [7:0] 	o_subfrom_clk_lev3 = o_subfrom_clk_lev2;
75   // verilator lint_on UNOPT
76
77   always @ (posedge clk) begin
78      cyc <= cyc+8'd1;
79      sepassign_in <= 0;
80      if (cyc == 8'd1) begin
81	 a_to_clk_levm3 <= 0;
82	 d_to_clk_levm2 <= 1;
83	 b_to_clk_levm1 <= 1;
84	 c_com_levs10 <= 2;
85	 sepassign_in <= 1;
86      end
87      if (cyc == 8'd2) begin
88	 if (sepassign !== 4'b1110) $stop;
89      end
90      if (cyc == 8'd3) begin
91
92	 $display("%d %d %d %d", m_from_clk_lev1_r,
93		  n_from_clk_lev2,
94		  o_from_com_levs11,
95		  o_from_comandclk_levs12);
96
97	 if (m_from_clk_lev1_r !== 8'h2) $stop;
98	 if (o_subfrom_clk_lev3 !== 8'h2) $stop;
99	 if (n_from_clk_lev2 !== 8'h2) $stop;
100	 if (o_from_com_levs11 !== 8'h3) $stop;
101	 if (o_from_com_levs13 !== 8'h5) $stop;
102	 if (o_from_comandclk_levs12 !== 8'h5) $stop;
103	 $write("*-* All Finished *-*\n");
104	 $finish;
105      end
106   end
107
108endmodule
109