1$version Generated by VerilatedVcd $end
2$date Fri Jun 22 19:27:45 2018
3 $end
4$timescale   1ps $end
5
6 $scope module top $end
7  $var wire  1 / clk $end
8  $scope module t $end
9   $var wire 32 % c1_count [31:0] $end
10   $var wire  1 # c1_start $end
11   $var wire 32 ( c3_count [31:0] $end
12   $var wire  1 ' c3_start $end
13   $var wire  1 / clk $end
14   $var wire  8 $ cyc [7:0] $end
15   $var wire 32 & s2_count [31:0] $end
16   $var wire  1 # s2_start $end
17   $scope module c1 $end
18    $var wire 32 % count [31:0] $end
19    $var wire 32 * runner [31:0] $end
20    $var wire 32 ) runnerm1 [31:0] $end
21    $var wire  1 # start $end
22   $upscope $end
23   $scope module c3 $end
24    $var wire 32 ( count [31:0] $end
25    $var wire 32 . runner [31:0] $end
26    $var wire 32 - runnerm1 [31:0] $end
27    $var wire  1 ' start $end
28   $upscope $end
29   $scope module s2 $end
30    $var wire 32 & count [31:0] $end
31    $var wire 32 , runner [31:0] $end
32    $var wire 32 + runnerm1 [31:0] $end
33    $var wire  1 # start $end
34   $upscope $end
35  $upscope $end
36 $upscope $end
37$enddefinitions $end
38
39
40#0
410#
42b00000000 $
43b00000000000000000000000000000000 %
44b00000000000000000000000000000000 &
450'
46b00000000000000000000000000000000 (
47b11111111111111111111111111111111 )
48b00000000000000000000000000000000 *
49b11111111111111111111111111111111 +
50b00000000000000000000000000000000 ,
51b11111111111111111111111111111111 -
52b00000000000000000000000000000000 .
530/
54#10
55b00000001 $
561/
57#15
580/
59#20
601#
61b00000010 $
62b00000000000000000000000000000011 %
63b00000000000000000000000000000011 &
641'
65b00000000000000000000000000000101 (
661/
67#25
680/
69#30
70b00000011 $
711/
72#35
730/
74#40
751/
76b00000100 $
77