1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2012 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7// see bug491
8
9package functions;
10   function real abs (real num);
11      abs = (num <0) ? -num : num;
12   endfunction
13   function real neg (real num);
14      return -abs(num);  // Check package funcs can call package funcs
15   endfunction
16endpackage
17
18module t ();
19   import functions::*;
20   localparam P = 1;
21   generate
22      if (P == 1) begin
23	 initial begin
24	    if (abs(-2.1) != 2.1) $stop;
25	    if (abs(2.2) != 2.2) $stop;
26	    if (neg(-2.1) != -2.1) $stop;
27	    if (neg(2.2) != -2.2) $stop;
28	    $write("*-* All Finished *-*\n");
29	    $finish;
30	 end
31      end
32   endgenerate
33endmodule
34