1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2009 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7package defs; 8 function automatic integer max; 9 input integer a; 10 input integer b; 11 max = (a > b) ? a : b; 12 endfunction 13 14 function automatic integer log2; 15 input integer value; 16 value = value >> 1; 17 for (log2 = 0; value > 0; log2 = log2 + 1) 18 value = value >> 1; 19 endfunction 20 21 function automatic integer ceil_log2; 22 input integer value; 23 value = value - 1; 24 for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1) 25 value = value >> 1; 26 endfunction 27endpackage 28 29module sub(); 30 31 import defs::*; 32 33 parameter RAND_NUM_MAX = ""; 34 35 localparam DATA_RANGE = RAND_NUM_MAX + 1; 36 localparam DATA_WIDTH = ceil_log2(DATA_RANGE); 37 localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1)); 38 39endmodule 40 41module t(/*AUTOARG*/ 42 // Inputs 43 clk 44 ); 45 46 import defs::*; 47 48 parameter WHICH = 0; 49 parameter MAX_COUNT = 10; 50 51 localparam MAX_EXPONENT = log2(MAX_COUNT); 52 localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1); 53 54 input clk; 55 56 generate 57 if (WHICH == 1) 58 begin : which_true 59 sub sub_true(); 60 defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT; 61 end 62 else 63 begin : which_false 64 sub sub_false(); 65 defparam sub_false.RAND_NUM_MAX = MAX_COUNT; 66 end 67 endgenerate 68 69endmodule 70