1// DESCRIPTION: Verilator: Verilog Test module
2//
3// IEEE 1800-2009 requires that any local definitions take precedence over
4// definitions in wildcard imported packages (section 26.3). Thus the code
5// below is valid SystemVerilog.
6//
7// This file ONLY is placed into the Public Domain, for any use, without
8// warranty, 2013 by Jie Xu.
9// SPDX-License-Identifier: CC0-1.0
10
11package defs;
12   parameter NUMBER = 8;
13   localparam NUM = NUMBER;
14endpackage
15
16
17module t(/*AUTOARG*/
18   // Inputs
19   clk
20   );
21
22   input clk;
23   import defs::*;
24
25   // This also fails if we use localparam
26   parameter NUM = 32;
27
28   // Check we have the right definition
29   always @(posedge clk) begin
30      if (NUM == 32) begin
31	 $write("*-* All Finished *-*\n");
32	 $finish;
33      end
34      else begin
35	 $stop;
36      end
37   end
38
39endmodule
40