1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2015 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t;
8   function integer bottom_4bits;
9      input [7:0] i;
10      bottom_4bits = 0;
11      bottom_4bits[3:0] = i[3:0];
12   endfunction
13
14   function integer bottom_2_unknown;
15      input [7:0] i;
16      // bottom_4bits = 0;  'x
17      bottom_2_unknown[1:0] = i[1:0];
18   endfunction
19
20   localparam p = bottom_4bits(8'h13);
21   localparam bu = bottom_2_unknown(8'h13);
22
23   initial begin
24      if (p != 3) $stop;
25      $write("*-* All Finished *-*\n");
26      $finish;
27   end
28endmodule
29