1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2013. 5// SPDX-License-Identifier: CC0-1.0 6 7// bug648 8 9module t (/*AUTOARG*/ 10 // Inputs 11 clk 12 ); 13 input clk; 14 15 integer cyc = 0; 16 reg [63:0] crc; 17 reg [63:0] sum; 18 19 // Take CRC data and apply to testblock inputs 20 wire [7:0] datai = crc[7:0]; 21 wire enable = crc[8]; 22 23 /*AUTOWIRE*/ 24 // Beginning of automatic wires (for undeclared instantiated-module outputs) 25 logic [7:0] datao; // From test of Test.v 26 // End of automatics 27 28 Test test (/*AUTOINST*/ 29 // Outputs 30 .datao (datao[7:0]), 31 // Inputs 32 .clk (clk), 33 .datai (datai[7:0]), 34 .enable (enable)); 35 36 // Aggregate outputs into a single result vector 37 wire [63:0] result = {56'h0, datao}; 38 39 // Test loop 40 always @ (posedge clk) begin 41`ifdef TEST_VERBOSE 42 $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); 43`endif 44 cyc <= cyc + 1; 45 crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; 46 sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; 47 if (cyc==0) begin 48 // Setup 49 crc <= 64'h5aef0c8d_d70a4497; 50 sum <= 64'h0; 51 end 52 else if (cyc<10) begin 53 sum <= 64'h0; 54 end 55 else if (cyc<90) begin 56 end 57 else if (cyc==99) begin 58 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); 59 if (crc !== 64'hc77bb9b3784ea091) $stop; 60 // What checksum will we end up with (above print should match) 61`define EXPECTED_SUM 64'h9d550d82d38926fa 62 if (sum !== `EXPECTED_SUM) $stop; 63 $write("*-* All Finished *-*\n"); 64 $finish; 65 end 66 end 67 68endmodule 69 70`define FAIL 1 71 72module Nested 73 ( 74 input logic clk, 75 input logic x, 76 output logic y 77 ); 78 logic t; 79 always_comb t = x ^ 1'b1; 80 81 always_ff @(posedge clk) begin 82 if (clk) 83 y <= t; 84 end 85endmodule 86 87module Test 88 ( 89 input logic clk, 90 input logic [7:0] datai, 91 input logic enable, 92 output logic [7:0] datao 93 ); 94 95 // verilator lint_off BLKANDNBLK 96 logic [7:0] datat; 97 // verilator lint_on BLKANDNBLK 98 99 for (genvar i = 0; i < 8; i++) begin 100 if (i%4 != 3) begin 101`ifndef FAIL 102 logic t; 103 always_comb begin 104 t = datai[i] ^ 1'b1; 105 end 106 always_ff @(posedge clk) begin 107 if (clk) 108 datat[i] <= t; 109 end 110`else 111 Nested nested_i 112 ( 113 .clk(clk), 114 .x(datai[i]), 115 .y(datat[i]) //<== via Vcellout wire 116 ); 117`endif 118 119 always_comb begin 120 casez (enable) 121 1'b1: datao[i] = datat[i]; 122 1'b0: datao[i] = '0; 123 default: datao[i] = 'x; 124 endcase 125 end 126 end 127 else begin 128 always_ff @(posedge clk) begin 129 if (clk) 130 datat[i] <= 0; //<== assign delayed 131 end 132 always_comb begin 133 casez (enable) 134 1'b1: datao[i] = datat[i] ^ 1'b1; 135 1'b0: datao[i] = '1; 136 default: datao[i] = 'x; 137 endcase 138 end 139 end 140 end 141endmodule 142