1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2017 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   a, y
10   );
11
12   input [1:0] a;
13   output [3:0] y;
14
15   Test #(.C(2))
16      test (.*);
17endmodule
18
19module Test
20  #(C = 3,
21    localparam O = 1 << C)
22   (input [C-1:0] a,
23    output reg [O-1:0] y);
24   initial begin
25      if (O != 4) $stop;
26      $write("*-* All Finished *-*\n");
27      $finish;
28   end
29endmodule
30