1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2015 by Johan Bjork 5// SPDX-License-Identifier: CC0-1.0 6 7module mod #( 8 parameter real HZ = 0 9); 10 //verilator no_inline_module 11 initial begin 12 if ((HZ-$floor(HZ)) - 0.45 > 0.01) $stop; 13 if ((HZ-$floor(HZ)) - 0.45 < -0.01) $stop; 14 end 15endmodule 16 17module t(); 18 mod #(.HZ(123.45)) mod1(); 19 mod #(.HZ(24.45)) mod2(); 20 21 initial begin 22 if (mod1.HZ != 123.45) $stop; 23 if (mod2.HZ != 24.45) $stop; 24 $write("*-* All Finished *-*\n"); 25 $finish; 26 end 27endmodule 28