1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2012 by Iztok Jeras. 5// SPDX-License-Identifier: CC0-1.0 6 7package tt_pkg; 8 typedef enum logic [1:0] {L0, L1, L2, L3} test_t; 9endpackage 10 11module t (/*AUTOARG*/ 12 // Outputs 13 ob 14 ); 15 16 output [1:0] ob; 17 18 import tt_pkg::*; 19 20 test_t a; 21 test_t b; 22 23 assign a = L0; 24 assign ob = b; 25 26 tt_buf #(.T_t(test_t)) 27 u_test 28 (.i(a), .o(b)); 29 30endmodule 31 32module tt_buf 33 #( 34 parameter type T_t = logic [0:0] 35 ) 36 ( 37 input T_t i, 38 output T_t o 39 ); 40 assign o = i; 41endmodule 42