1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2020 by Peter Monsson. 5 6module t (/*AUTOARG*/ 7 // Inputs 8 clk 9 ); 10 11 input clk; 12 integer cyc; initial cyc=1; 13 wire [31:0] in = cyc; 14 15 Test test (/*AUTOINST*/ 16 // Inputs 17 .clk (clk), 18 .in (in[31:0])); 19 20 Test2 test2 (/*AUTOINST*/ 21 // Inputs 22 .clk (clk), 23 .in (in[31:0])); 24 25 always @ (posedge clk) begin 26 if (cyc!=0) begin 27 cyc <= cyc + 1; 28 if (cyc==10) begin 29 $write("*-* All Finished *-*\n"); 30 $finish; 31 end 32 end 33 end 34 35endmodule 36 37module Test (/*AUTOARG*/ 38 // Inputs 39 clk, in 40 ); 41 42 input clk; 43 input [31:0] in; 44 45 reg [31:0] dly0 = 0; 46 reg [31:0] dly1 = 1; 47 reg [31:0] dly2 = -1; 48 49 // If called in an assertion, sequence, or property, the appropriate clocking event. 50 // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. 51 // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. 52 // Otherwise, if called in a procedure, the inferred clock 53 // Otherwise, default clocking 54 55 always @(posedge clk) begin 56 dly0 <= in; 57 dly1 <= in; 58 dly2 <= in; 59 // In clock expression 60 $write("in=%0d, dly0=%0d, rose=%0d, past=%0d\n", in, dly0, $rose(dly0), $past(dly0)); 61 if ($rose(dly0[4])) $stop; 62 if ($fell(dly1[4])) $stop; 63 if ($stable(dly2)) $stop; 64 if (!$changed(dly2)) $stop; 65 end 66 67 assert property (@(posedge clk) $rose(dly0) || dly0%2==0); 68 assert property (@(posedge clk) $fell(dly1) || dly1%2==1); 69 assert property (@(posedge clk) !$stable(dly2)); 70 assert property (@(posedge clk) $changed(dly2)); 71endmodule 72 73 74module Test2 (/*AUTOARG*/ 75 // Inputs 76 clk, in 77 ); 78 79 input clk; 80 input [31:0] in; 81 82 reg [31:0] dly0; 83 reg [31:0] dly1 = 1; 84 reg [31:0] dly2; 85 86 always @(posedge clk) begin 87 dly0 <= in; 88 dly1 <= in; 89 dly2 <= in; 90 if ($rose(dly0[31:4])) $stop; 91 if ($fell(dly1[31:4])) $stop; 92 if (!$stable(dly2[31:4])) $stop; 93 if ($changed(dly2[31:4])) $stop; 94 end 95 96 default clocking @(posedge clk); endclocking 97 assert property ($rose(dly0[0]) || dly0%2==0); 98 99 default clocking @(posedge clk); endclocking 100 assert property ($fell(dly1[0]) || dly1%2==1); 101 102 default clocking @(posedge clk); endclocking 103 assert property ($stable(dly2[31:4])); 104 assert property (!$changed(dly2[31:4])); 105endmodule 106