1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2018 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (d, clk); 8 input d; 9 input clk; 10 11 always @ (posedge clk) begin 12 // Unsupported 13 if ($past(d, 0, 0)) $stop; 14 if ($past(d, 0, 0, clk)) $stop; 15 if ($fell(d, clk)) $stop; 16 if ($rose(d, clk)) $stop; 17 if ($stable(d, clk)) $stop; 18 if ($changed(d, clk)) $stop; 19 end 20endmodule 21