1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2010 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7//===========================================================================
8// Includes
9
10
11example line 10;
12example line 11;
13
14`include "t_pipe_filter_inc.vh"
15// Twice to check caching of includes
16`include "t_pipe_filter_inc.vh"
17
18example line 15;
19example line 16;
20