1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Geza Lore.
5// SPDX-License-Identifier: CC0-1.0
6
7`define show(x) $display("oarray[%2d] is %2d", x, oarray[x])
8
9module t (/*AUTOARG*/);
10
11   int iarray [63:0];
12   int oarray [63:0];
13
14   initial begin
15      for (int i = 0; i < 64 ; i = i + 1) begin
16        iarray[i] = i;
17        oarray[i] = 0;
18      end
19
20      for (int i = 0; i < 63; i = i + 1) begin
21        oarray[i] = iarray[i + 1];
22      end
23
24      $display("shift down 1");
25      `show(63);
26      `show(62);
27      `show(61);
28      `show(32);
29      `show(2);
30      `show(1);
31      `show(0);
32
33      for (int i = 63; i >= 2 ; i = i - 1) begin
34        oarray[i] = iarray[i - 2];
35      end
36
37      $display("shift up 2");
38      `show(63);
39      `show(62);
40      `show(61);
41      `show(32);
42      `show(2);
43      `show(1);
44      `show(0);
45
46      $write("*-* All Finished *-*\n");
47      $finish;
48   end
49
50endmodule
51