1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2017 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk, d0, d1 10 ); 11 12 input clk; 13 input [7:0] d0, d1; 14 15 logic [7:0] inia [1:0][3:0] = '{ '{ '0, '1, 8'hfe, 8'hed }, 16 '{ '1, '1, 8'h11, 8'h22 }}; 17 logic [7:0] inil [0:1][0:3] = '{ '{ '0, '1, 8'hfe, 8'hed }, 18 '{ '1, '1, 8'h11, 8'h22 }}; 19 20 logic [7:0] data [1:0][3:0]; 21 logic [7:0] datl [0:1][0:3]; 22 23 initial begin 24 data = '{ '{ d0, d1, 8'hfe, 8'hed }, 25 '{ d1, d1, 8'h11, 8'h22 }}; 26 data[0] = '{ d0, d1, 8'h19, 8'h39 }; 27 28 datl = '{ '{ d0, d1, 8'hfe, 8'hed }, 29 '{ d1, d1, 8'h11, 8'h22 }}; 30 datl[0] = '{ d0, d1, 8'h19, 8'h39 }; 31 32`ifdef TEST_VERBOSE 33 $display("D=%x %x %x %x -> 39 19 x x", data[0][0], data[0][1], data[0][2], data[0][3]); 34 $display("D=%x %x %x %x -> ed fe x x", data[1][0], data[1][1], data[1][2], data[1][3]); 35 $display("L=%x %x %x %x -> x x 19 39", datl[0][0], datl[0][1], datl[0][2], datl[0][3]); 36 $display("L=%x %x %x %x -> x x 11 12", datl[1][0], datl[1][1], datl[1][2], datl[1][3]); 37`endif 38 if (inia[0][0] !== 8'h22) $stop; 39 if (inia[0][1] !== 8'h11) $stop; 40 if (inia[1][0] !== 8'hed) $stop; 41 if (inia[1][1] !== 8'hfe) $stop; 42 43 if (inil[0][2] !== 8'hfe) $stop; 44 if (inil[0][3] !== 8'hed) $stop; 45 if (inil[1][2] !== 8'h11) $stop; 46 if (inil[1][3] !== 8'h22) $stop; 47 48 if (data[0][0] !== 8'h39) $stop; 49 if (data[0][1] !== 8'h19) $stop; 50 if (data[1][0] !== 8'hed) $stop; 51 if (data[1][1] !== 8'hfe) $stop; 52 53 if (datl[0][2] !== 8'h19) $stop; 54 if (datl[0][3] !== 8'h39) $stop; 55 if (datl[1][2] !== 8'h11) $stop; 56 if (datl[1][3] !== 8'h22) $stop; 57 $write("*-* All Finished *-*\n"); 58 $finish; 59 end 60endmodule 61