1//////////////////////////////////////////////////////////////////////////////// 2// // 3// This file is placed into the Public Domain, for any use, without warranty. // 4// 2012 by Iztok Jeras // 5// SPDX-License-Identifier: CC0-1.0 // 6// // 7//////////////////////////////////////////////////////////////////////////////// 8 9import package_bus::*; 10import package_str::*; 11import package_uni::*; 12 13module sv_bus_mux_demux_mux ( 14 // system signals 15 input logic clk, // clock 16 input logic rst, // reset 17 // input bus 18 input logic bus_vld, // valid (chip select) 19 input logic [31:0] bus_adr, // address 20 input logic [31:0] bus_dat, // data 21 output logic bus_rdy, // ready (acknowledge) 22 // output stream 23 output logic str_vld, // valid (chip select) 24 output logic [7:0] str_bus, // byte data bus 25 input logic str_rdy // ready (acknowledge) 26); 27 28logic bus_trn; // bus data transfer 29logic str_trn; // stream data transfer 30 31logic [2:0] pkt_cnt; // packet byte counter 32logic pkt_end; // packet byte counter end 33 34//t_bus pkt_bus; // transfer packet as a structure 35//t_str pkt_str; // transfer packet as an array 36t_uni pkt_uni; // transfer packet as an union 37 38// bus data transfer 39assign bus_trn = bus_vld & bus_rdy; 40 41// ready if pipe is empty or output is ready 42assign bus_rdy = ~str_vld | pkt_end; 43 44// writing input address/data into a structure 45always @ (posedge clk) 46if (bus_trn) begin 47 pkt_uni.bus.adr <= bus_adr; 48 pkt_uni.bus.dat <= bus_dat; 49end 50 51// output valid is set by an input transfer 52// or cleared by the last output transfer 53always @ (posedge clk, posedge rst) 54if (rst) str_vld <= 1'b0; 55else str_vld <= bus_trn | (str_vld & ~pkt_end); 56 57// packet byte counter 58always @ (posedge clk, posedge rst) 59if (rst) pkt_cnt <= '0; 60else if (str_trn) pkt_cnt <= pkt_cnt + 3'd1; 61 62// packet byte counter end 63assign pkt_end = str_rdy & (&pkt_cnt); 64 65// TODO, this should be a registered signal 66assign str_bus = pkt_uni.str [pkt_cnt]; 67 68// stream data transfer 69assign str_trn = str_vld & str_rdy; 70 71endmodule : sv_bus_mux_demux_mux 72