1// DESCRIPTION: Verilator: Large test for SystemVerilog 2 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2012. 5// SPDX-License-Identifier: CC0-1.0 6 7// Contributed by M W Lund, Atmel Corporation. 8 9module ac 10 #( parameter 11 ID = 1 ) 12 ( 13 // *************************************************************************** 14 // Module Interface (interfaces, outputs, and inputs) 15 // *************************************************************************** 16 17 // **** Interfaces **** 18 genbus_if.slave dbus, 19 pads_if.mp_ana padsif, 20 21 // - System - 22 input logic clk, 23 input logic rst 24 ); 25 26 // *************************************************************************** 27 // Regs and Wires, Automatics 28 // *************************************************************************** 29 30 /*AUTOWIRE*/ 31 // Beginning of automatic wires (for undeclared instantiated-module outputs) 32 logic acenable; // From i_ac_dig of ac_dig.v 33 logic acout; // From i_ac_ana of ac_ana.v 34 // End of automatics 35 36 37 // *************************************************************************** 38 // Digital Control 39 // *************************************************************************** 40 41 ac_dig 42 #( .ID(ID) ) 43 i_ac_dig 44 ( 45 .dbus (dbus), 46 /*AUTOINST*/ 47 // Outputs 48 .acenable (acenable), 49 // Inputs 50 .acout (acout), 51 .clk (clk), 52 .rst (rst)); 53 54 55 // *************************************************************************** 56 // Analog Model 57 // *************************************************************************** 58 59 ac_ana 60 i_ac_ana 61 ( 62 .padsif (padsif), 63 /*AUTOINST*/ 64 // Outputs 65 .acout (acout), 66 // Inputs 67 .acenable (acenable), 68 .clk (clk), 69 .rst (rst)); 70 71endmodule // ac 72