1// DESCRIPTION: Verilator: Large test for SystemVerilog
2
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2012.
5// SPDX-License-Identifier: CC0-1.0
6
7// Contributed by M W Lund, Atmel Corporation.
8
9module ac_ana
10// #( parameter
11//      ID = 1 )
12 (
13  // ***************************************************************************
14  // Module Interface (interfaces, outputs, and inputs)
15  // ***************************************************************************
16
17  // **** Interfaces ****
18  pads_if.mp_ana  padsif,
19
20
21  // **** Outputs ****
22  output logic       acout,
23
24
25  // **** Inputs ****
26  input  logic       acenable,
27
28
29  // - System -
30  input  logic       clk,
31  input  logic       rst
32 );
33
34  // ***************************************************************************
35  // Analog Model
36  // ***************************************************************************
37
38  assign acout = (padsif.ana[1] - padsif.ana[2]) & acenable;
39
40  assign padsif.ana_override[1] = 1'b0;
41  assign padsif.ana_override[2] = 1'b0;
42
43
44endmodule // ac_ana
45