1// DESCRIPTION: Verilator: Large test for SystemVerilog 2 3// This file ONLY is placed into the Public Domain, for any use, 4// without warranty, 2012. 5// SPDX-License-Identifier: CC0-1.0 6 7// Contributed by M W Lund, Atmel Corporation. 8 9module ac_dig 10 #( parameter 11 ID = 1 ) 12 ( 13 // *************************************************************************** 14 // Module Interface (interfaces, outputs, and inputs) 15 // *************************************************************************** 16 17 // **** Interfaces **** 18 genbus_if.slave dbus, 19 20 21 // **** Outputs **** 22 output logic acenable, 23 24 25 // **** Inputs **** 26 input logic acout, 27 28 29 // - System - 30 input logic clk, 31 input logic rst 32 ); 33 34 // *************************************************************************** 35 // Regs and Wires 36 // *************************************************************************** 37 38 // **** Internal Data Bus **** 39 logic [15:0] sdata; 40 logic ws; 41 logic [15:0] mdata; 42 logic [15:0] adr; 43 logic [1:0] we; 44 logic [1:0] re; 45 46 47 // **** User Registers **** 48 struct packed 49 { 50 logic [7:1] reserved; 51 logic enable; 52 } control; 53 54 struct packed 55 { 56 logic [7:1] reserved; 57 logic acout; 58 } status; 59 60 61 // **** Internals **** 62 logic [1:0] sync; 63 64 65 // *************************************************************************** 66 // Assignments 67 // *************************************************************************** 68 69 assign acenable = control.enable; 70 71 72 73 // *************************************************************************** 74 // "dbus" Connection 75 // *************************************************************************** 76 77 always_comb 78 begin 79`ifdef VERILATOR //TODO 80 dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr ), .we(we), .re(re) ); 81`else 82 dbus.sConnect( .id(ID), .rst(rst), .sdata(sdata), .ws(ws), .mdata(mdata), .adr(adr[1:0]), .we(we), .re(re) ); 83`endif 84// dbus.sConnect( ID, rst, sdata, ws, mdata, adr, we, re ); 85 end 86 87 88 89 // *************************************************************************** 90 // Register Access 91 // *************************************************************************** 92 93 // **** Register Write **** 94 always_ff @( posedge clk ) 95 begin 96 if ( rst ) 97 control <= 8'h00; 98 else if ( (adr[1:0] == 2'b00) & we[0] ) 99 control <= mdata[7:0]; 100 end 101 102 103 // **** Regiser Read **** 104 always_comb 105 begin: RegisterRead 106 // - Local Variables - 107 logic [7:0] data[0:3]; // Read access concatination. 108 109 // - Setup read multiplexer - 110 data = '{ control, 111 status, 112 8'h00, 113 8'h00 }; 114 115 // - Connect "genbusif" - 116 sdata = { 8'h00, data[ adr[1:0] ] }; 117 ws = 1'b0; 118 end 119 120 121 122 // *************************************************************************** 123 // Status 124 // *************************************************************************** 125 126 // **** Synchronization **** 127 always_ff @( posedge clk ) 128 begin 129 if ( rst ) 130 sync <= 2'b00; 131 else if ( control.enable ) 132 sync <= {sync[0], acout}; 133 end 134 135 always_comb 136 begin 137 // - Defaults - 138 status = {$size(status){1'b0}}; 139 140 // - Set register values - 141 status.acout = sync[1]; 142 end 143 144endmodule // ac_dig 145