1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Geza Lore.
5// SPDX-License-Identifier: CC0-1.0
6
7module t #(
8           parameter [0:7] P = 8'd10
9           )(/*AUTOARG*/
10   // Inputs
11   clk
12   );
13   input clk;
14   int   cyc = 0;
15
16   localparam [0:7] Q = 8'd20;
17
18   logic [   0:  0] v_a = '0;
19   logic [   0:  1] v_b = '0;
20   logic [   0:  7] v_c = '0;
21   logic [   0:  8] v_d = '0;
22   logic [   0: 15] v_e = '0;
23   logic [   0: 16] v_f = '0;
24   logic [   0: 31] v_g = '0;
25   logic [   0: 32] v_h = '0;
26   logic [   0: 63] v_i = '0;
27   logic [   0: 64] v_j = '0;
28   logic [   0:127] v_k = '0;
29   logic [   0:128] v_l = '0;
30   logic [   0:255] v_m = '0;
31   logic [   0:256] v_n = '0;
32   logic [   0:511] v_o = '0;
33   logic [  -1:  1] v_p = '0;
34   logic [  -7:  7] v_q = '0;
35   logic [ -15: 15] v_r = '0;
36   logic [ -31: 31] v_s = '0;
37   logic [ -63: 63] v_t = '0;
38   logic [-127:127] v_u = '0;
39   logic [-255:255] v_v = '0;
40
41   always @(posedge clk) begin
42      if (cyc == 0) begin
43         v_a <= '1;
44         v_b <= '1;
45         v_c <= '1;
46         v_d <= '1;
47         v_e <= '1;
48         v_f <= '1;
49         v_g <= '1;
50         v_h <= '1;
51         v_i <= '1;
52         v_j <= '1;
53         v_k <= '1;
54         v_l <= '1;
55         v_m <= '1;
56         v_n <= '1;
57         v_o <= '1;
58         v_p <= '1;
59         v_q <= '1;
60         v_r <= '1;
61         v_s <= '1;
62         v_t <= '1;
63         v_u <= '1;
64         v_v <= '1;
65      end else begin
66         v_a <= v_a << 1;
67         v_b <= v_b << 1;
68         v_c <= v_c << 1;
69         v_d <= v_d << 1;
70         v_e <= v_e << 1;
71         v_f <= v_f << 1;
72         v_g <= v_g << 1;
73         v_h <= v_h << 1;
74         v_i <= v_i << 1;
75         v_j <= v_j << 1;
76         v_k <= v_k << 1;
77         v_l <= v_l << 1;
78         v_m <= v_m << 1;
79         v_n <= v_n << 1;
80         v_o <= v_o << 1;
81         v_p <= v_p << 1;
82         v_q <= v_q << 1;
83         v_r <= v_r << 1;
84         v_s <= v_s << 1;
85         v_t <= v_t << 1;
86         v_u <= v_u << 1;
87         v_v <= v_v << 1;
88      end
89
90      cyc <= cyc + 1;
91      if (cyc == 2) begin
92         $write("*-* All Finished *-*\n");
93         $finish;
94      end
95   end
96
97endmodule
98