1// DESCRIPTION: Verilator: Unsupported tristate construct error
2//
3// This is a compile only regression test of tristate handling for bug514
4//
5// This file ONLY is placed into the Public Domain, for any use,
6// without warranty, 2017 by Rob Stoddard.
7// SPDX-License-Identifier: CC0-1.0
8
9module t (/*AUTOARG*/
10   // Outputs
11   out,
12   // Inputs
13   data, up_down, clk, reset
14   );
15
16   //----------Output Ports--------------
17   output [7:0] out;
18   //------------Input Ports--------------
19   //input [7:0] data ;
20   input [7:0] 	data;
21   input 	up_down, clk, reset;
22   //------------Internal Variables--------
23   reg [7:0] 	out;
24   logic [7:0] 	q_out;
25
26   //-------------Code Starts Here-------
27   always @(posedge clk)
28     if (reset) begin // active high reset
29        out <= 8'b0 ;
30     end else if (up_down) begin
31        out <= out + 1;
32     end else begin
33        out <= q_out;
34     end
35
36   // verilator lint_off PINMISSING
37   sub_mod sub_mod
38     (
39      .clk(clk),
40      .data(data),
41      .reset(reset),
42      .q(q_out)
43      );
44   // verilator lint_on PINMISSING
45
46endmodule
47
48module sub_mod (/*AUTOARG*/
49   // Outputs
50   q, test_out,
51   // Inouts
52   test_inout,
53   // Inputs
54   data, clk, reset
55   );
56
57   //-----------Input Ports---------------
58
59   input [7:0] data /*verilator public*/;
60   input       clk, reset;
61   inout       test_inout;  // Get rid of this, the problem goes away.
62
63   //-----------Output Ports---------------
64   output [7:0] q;
65   output 	test_out;  // Not assigned,  no problem.
66
67   logic [7:0] 	que;
68
69   // Uncomment this line, the error goes away.
70   //assign test_inout = que;
71
72   assign q = que;
73   always @ ( posedge clk)
74     if (~reset) begin
75        que <= 8'b0;
76     end else begin
77        que <= data;
78     end
79endmodule
80