1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2018 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (clk);
8   input clk;
9
10   tri [3:0] w;
11
12   pullup p0 (w[0]);
13   pulldown p1 (w[1]);
14   pulldown p2 (w[2]);
15   pullup p3 (w[3]);
16
17   always_ff @ (posedge clk) begin
18      if (w != 4'b1001) $stop;
19      $write("*-* All Finished *-*\n");
20      $finish;
21   end
22endmodule
23