1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2021 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7package pkg;
8   parameter [7:0] WIDTH = 8;
9   typedef logic [WIDTH-1:0] SZ;
10endpackage // pkg
11
12module t
13  import pkg::*;
14   # (parameter type SZ = SZ)
15   (input SZ i,
16    output SZ o);
17
18   always_comb o = i;
19
20endmodule
21