test_regress/t/t_typedef_circ_bad.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

typedef a_t;
typedef a_t b_t;
typedef b_t a_t;