1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/);
8
9   generate
10      begin
11         eh2_ram dccm_bank (.*);
12      end
13      begin
14         eh2_ram dccm_bank (.*);  // Error: duplicate
15      end
16   endgenerate
17
18endmodule
19
20module eh2_ram ();
21endmodule
22