1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2018 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7// Make sure type errors aren't suppressable 8// verilator lint_off WIDTH 9 10module t(ref int bad_primary_ref 11 /*AUTOARG*/); 12endmodule 13