1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2005 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7// verilator lint_off SYMRSVDWORD 8 9module t (/*AUTOARG*/ 10 // Inputs 11 bool 12 ); 13 14 input bool; // BAD 15 16 reg vector; // OK, as not public 17 reg switch /*verilator public*/; // Bad 18 19 typedef struct packed { 20 logic [31:0] vector; // OK, as not public 21 } test; 22 test t; 23 24 // global is a 1800-2009 reserved word, but we allow it when possible. 25 reg global; 26 27 initial begin 28 t.vector = 1; 29 $write("*-* All Finished *-*\n"); 30 $finish; 31 end 32 33endmodule 34