1// DESCRIPTION: Verilator: Verilog Test module 2// 3// Copyright 2010 by Wilson Snyder. This program is free software; you can 4// redistribute it and/or modify it under the terms of either the GNU 5// Lesser General Public License Version 3 or the Perl Artistic License 6// Version 2.0. 7// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 8 9`ifdef VERILATOR 10//We call it via $c so we can verify DPI isn't required - see bug572 11`else 12import "DPI-C" context function int mon_check(); 13`endif 14 15module t (/*AUTOARG*/ 16 // Inputs 17 clk 18 ); 19 20`ifdef VERILATOR 21`systemc_header 22extern "C" int mon_check(); 23`verilog 24`endif 25 26 input clk; 27 28 reg onebit /*verilator public_flat_rw @(posedge clk) */; 29 30 integer status; 31 32 // Test loop 33 initial begin 34`ifdef VERILATOR 35 status = $c32("mon_check()"); 36`else 37 status = mon_check(); 38`endif 39 $write("*-* All Finished *-*\n"); 40 $finish; 41 end 42 43endmodule : t 44