1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2012 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t_waiveroutput;
8
9   reg width_warn = 2'b11;  // Width warning - must be line 18
10endmodule
11