1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2008 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module foo(input logic i_clk); /* verilator no_inline_module */
8endmodule
9
10// --flatten forces inlining of 'no_inline_module' module foo.
11module top(input logic i_clk);
12  foo f(.*);
13endmodule
14