1/*
2 *  yosys -- Yosys Open SYnthesis Suite
3 *
4 *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
5 *
6 *  Permission to use, copy, modify, and/or distribute this software for any
7 *  purpose with or without fee is hereby granted, provided that the above
8 *  copyright notice and this permission notice appear in all copies.
9 *
10 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20module VCC (output V);
21   assign V = 1'b1;
22endmodule // VCC
23
24module GND (output G);
25   assign G = 1'b0;
26endmodule // GND
27
28/* Altera MAX10 devices Input Buffer Primitive */
29module fiftyfivenm_io_ibuf
30  (output o, input i, input ibar);
31   assign ibar = ibar;
32   assign o    = i;
33endmodule // fiftyfivenm_io_ibuf
34
35/* Altera MAX10 devices Output Buffer Primitive */
36module fiftyfivenm_io_obuf
37  (output o, input i, input oe);
38   assign o  = i;
39   assign oe = oe;
40endmodule // fiftyfivenm_io_obuf
41
42/* Altera MAX10 4-input non-fracturable LUT Primitive */
43module fiftyfivenm_lcell_comb
44  (output combout, cout,
45   input dataa, datab, datac, datad, cin);
46
47   /* Internal parameters which define the behaviour
48    of the LUT primitive.
49    lut_mask define the lut function, can be expressed in 16-digit bin or hex.
50    sum_lutc_input define the type of LUT (combinational | arithmetic).
51    dont_touch for retiming || carry options.
52    lpm_type for WYSIWYG */
53
54   parameter lut_mask = 16'hFFFF;
55   parameter dont_touch = "off";
56   parameter lpm_type = "fiftyfivenm_lcell_comb";
57   parameter sum_lutc_input = "datac";
58
59   reg [1:0] lut_type;
60   reg       cout_rt;
61   reg       combout_rt;
62   wire      dataa_w;
63   wire      datab_w;
64   wire      datac_w;
65   wire      datad_w;
66   wire      cin_w;
67
68   assign dataa_w = dataa;
69   assign datab_w = datab;
70   assign datac_w = datac;
71   assign datad_w = datad;
72
73   function lut_data;
74      input [15:0] mask;
75      input        dataa, datab, datac, datad;
76      reg [7:0]    s3;
77      reg [3:0]    s2;
78      reg [1:0]    s1;
79      begin
80         s3 = datad ? mask[15:8] : mask[7:0];
81         s2 = datac ?   s3[7:4]  :   s3[3:0];
82         s1 = datab ?   s2[3:2]  :   s2[1:0];
83         lut_data = dataa ? s1[1] : s1[0];
84      end
85
86   endfunction
87
88   initial begin
89      if (sum_lutc_input == "datac") lut_type = 0;
90      else
91        if (sum_lutc_input == "cin")   lut_type = 1;
92        else begin
93           $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
94           $finish();
95        end
96   end
97
98   always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
99      if (lut_type == 0) begin // logic function
100         combout_rt = lut_data(lut_mask, dataa_w, datab_w,
101                               datac_w, datad_w);
102      end
103      else if (lut_type == 1) begin // arithmetic function
104         combout_rt = lut_data(lut_mask, dataa_w, datab_w,
105                               cin_w, datad_w);
106      end
107      cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
108   end
109
110   assign combout = combout_rt & 1'b1;
111   assign cout = cout_rt & 1'b1;
112
113endmodule // fiftyfivenm_lcell_comb
114
115/* Altera D Flip-Flop Primitive */
116module dffeas
117  (output q,
118   input d, clk, clrn, prn, ena,
119   input asdata, aload, sclr, sload);
120
121   // Timing simulation is not covered
122   parameter power_up="dontcare";
123   parameter is_wysiwyg="false";
124
125   reg   q_tmp;
126   wire  reset;
127   reg [7:0] debug_net;
128
129   assign reset       = (prn && sclr && ~clrn && ena);
130   assign q           = q_tmp & 1'b1;
131
132   always @(posedge clk, posedge aload) begin
133      if(reset)        q_tmp <= 0;
134      else q_tmp <= d;
135   end
136   assign q = q_tmp;
137
138endmodule // dffeas
139
140/* MAX10 altpll clearbox model */
141(* blackbox *)
142module fiftyfivenm_pll
143  (inclk,
144   fbin,
145   fbout,
146   clkswitch,
147   areset,
148   pfdena,
149   scanclk,
150   scandata,
151   scanclkena,
152   configupdate,
153   clk,
154   phasecounterselect,
155   phaseupdown,
156   phasestep,
157   clkbad,
158   activeclock,
159   locked,
160   scandataout,
161   scandone,
162   phasedone,
163   vcooverrange,
164   vcounderrange);
165
166   parameter operation_mode                = "normal";
167   parameter pll_type                      = "auto";
168   parameter compensate_clock              = "clock0";
169   parameter inclk0_input_frequency        = 0;
170   parameter inclk1_input_frequency        = 0;
171   parameter self_reset_on_loss_lock       = "off";
172   parameter switch_over_type              = "auto";
173   parameter switch_over_counter           = 1;
174   parameter enable_switch_over_counter    = "off";
175   parameter bandwidth                     = 0;
176   parameter bandwidth_type                = "auto";
177   parameter use_dc_coupling               = "false";
178   parameter lock_high = 0;
179   parameter lock_low = 0;
180   parameter lock_window_ui                = "0.05";
181   parameter test_bypass_lock_detect       = "off";
182   parameter clk0_output_frequency         = 0;
183   parameter clk0_multiply_by              = 0;
184   parameter clk0_divide_by                = 0;
185   parameter clk0_phase_shift              = "0";
186   parameter clk0_duty_cycle               = 50;
187   parameter clk1_output_frequency         = 0;
188   parameter clk1_multiply_by              = 0;
189   parameter clk1_divide_by                = 0;
190   parameter clk1_phase_shift              = "0";
191   parameter clk1_duty_cycle               = 50;
192   parameter clk2_output_frequency         = 0;
193   parameter clk2_multiply_by              = 0;
194   parameter clk2_divide_by                = 0;
195   parameter clk2_phase_shift              = "0";
196   parameter clk2_duty_cycle               = 50;
197   parameter clk3_output_frequency         = 0;
198   parameter clk3_multiply_by              = 0;
199   parameter clk3_divide_by                = 0;
200   parameter clk3_phase_shift              = "0";
201   parameter clk3_duty_cycle               = 50;
202   parameter clk4_output_frequency         = 0;
203   parameter clk4_multiply_by              = 0;
204   parameter clk4_divide_by                = 0;
205   parameter clk4_phase_shift              = "0";
206   parameter clk4_duty_cycle               = 50;
207   parameter pfd_min                       = 0;
208   parameter pfd_max                       = 0;
209   parameter vco_min                       = 0;
210   parameter vco_max                       = 0;
211   parameter vco_center                    = 0;
212   // Advanced user parameters
213   parameter m_initial = 1;
214   parameter m = 0;
215   parameter n = 1;
216   parameter c0_high = 1;
217   parameter c0_low = 1;
218   parameter c0_initial = 1;
219   parameter c0_mode = "bypass";
220   parameter c0_ph = 0;
221   parameter c1_high = 1;
222   parameter c1_low = 1;
223   parameter c1_initial = 1;
224   parameter c1_mode = "bypass";
225   parameter c1_ph = 0;
226   parameter c2_high = 1;
227   parameter c2_low = 1;
228   parameter c2_initial = 1;
229   parameter c2_mode = "bypass";
230   parameter c2_ph = 0;
231   parameter c3_high = 1;
232   parameter c3_low = 1;
233   parameter c3_initial = 1;
234   parameter c3_mode = "bypass";
235   parameter c3_ph = 0;
236   parameter c4_high = 1;
237   parameter c4_low = 1;
238   parameter c4_initial = 1;
239   parameter c4_mode = "bypass";
240   parameter c4_ph = 0;
241   parameter m_ph = 0;
242   parameter clk0_counter = "unused";
243   parameter clk1_counter = "unused";
244   parameter clk2_counter = "unused";
245   parameter clk3_counter = "unused";
246   parameter clk4_counter = "unused";
247   parameter c1_use_casc_in = "off";
248   parameter c2_use_casc_in = "off";
249   parameter c3_use_casc_in = "off";
250   parameter c4_use_casc_in = "off";
251   parameter m_test_source  = -1;
252   parameter c0_test_source = -1;
253   parameter c1_test_source = -1;
254   parameter c2_test_source = -1;
255   parameter c3_test_source = -1;
256   parameter c4_test_source = -1;
257   parameter vco_multiply_by = 0;
258   parameter vco_divide_by = 0;
259   parameter vco_post_scale = 1;
260   parameter vco_frequency_control = "auto";
261   parameter vco_phase_shift_step = 0;
262   parameter charge_pump_current = 10;
263   parameter loop_filter_r = "1.0";
264   parameter loop_filter_c = 0;
265   parameter pll_compensation_delay = 0;
266   parameter lpm_type = "fiftyfivenm_pll";
267   parameter phase_counter_select_width = 3;
268
269   input [1:0] inclk;
270   input       fbin;
271   input       clkswitch;
272   input       areset;
273   input       pfdena;
274   input [phase_counter_select_width - 1:0] phasecounterselect;
275   input                                    phaseupdown;
276   input                                    phasestep;
277   input                                    scanclk;
278   input                                    scanclkena;
279   input                                    scandata;
280   input                                    configupdate;
281   output [4:0]                             clk;
282   output [1:0]                             clkbad;
283   output                                   activeclock;
284   output                                   locked;
285   output                                   scandataout;
286   output                                   scandone;
287   output                                   fbout;
288   output                                   phasedone;
289   output                                   vcooverrange;
290   output                                   vcounderrange;
291
292endmodule // cycloneive_pll
293