1read_verilog ../common/adffs.v 2design -save read 3 4hierarchy -top adff 5proc 6equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check 7design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 8cd adff # Constrain all select calls below inside the top module 9stat 10select -assert-count 1 t:DFFC 11select -assert-count 3 t:IBUF 12select -assert-count 1 t:OBUF 13 14select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D 15 16 17design -load read 18hierarchy -top adffn 19proc 20equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check 21design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 22cd adffn # Constrain all select calls below inside the top module 23select -assert-count 1 t:DFFC 24select -assert-count 1 t:LUT1 25select -assert-count 3 t:IBUF 26select -assert-count 1 t:OBUF 27 28select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D 29 30 31design -load read 32hierarchy -top dffs 33proc 34equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check 35design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 36cd dffs # Constrain all select calls below inside the top module 37select -assert-count 1 t:DFF 38select -assert-count 1 t:LUT2 39select -assert-count 4 t:IBUF 40select -assert-count 1 t:OBUF 41 42select -assert-none t:DFF t:LUT2 t:IBUF t:OBUF %% t:* %D 43 44 45design -load read 46hierarchy -top ndffnr 47proc 48equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check 49design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 50cd ndffnr # Constrain all select calls below inside the top module 51select -assert-count 1 t:DFFNR 52select -assert-count 1 t:LUT1 53select -assert-count 4 t:IBUF 54select -assert-count 1 t:OBUF 55 56select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D 57