1read_verilog ../common/counter.v 2hierarchy -top top 3proc 4flatten 5equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check 6design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 7cd top # Constrain all select calls below inside the top module 8select -assert-count 1 t:LUT1 9select -assert-count 3 t:LUT2 10select -assert-count 5 t:LUT3 11select -assert-count 1 t:LUT4 12select -assert-count 8 t:dffepc 13select -assert-count 1 t:logic_0 14select -assert-count 1 t:logic_1 15select -assert-count 8 t:outpad 16select -assert-count 2 t:ckpad 17 18select -assert-none t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:outpad t:ckpad %% t:* %D 19