1read_verilog ../common/latches.v 2design -save read 3 4hierarchy -top latchp 5proc 6# Can't run any sort of equivalence check because latches are blown to LUTs 7synth_quicklogic 8cd latchp # Constrain all select calls below inside the top module 9select -assert-count 1 t:LUT3 10select -assert-count 3 t:inpad 11select -assert-count 1 t:outpad 12 13select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D 14 15 16design -load read 17hierarchy -top latchn 18proc 19# Can't run any sort of equivalence check because latches are blown to LUTs 20synth_quicklogic 21cd latchn # Constrain all select calls below inside the top module 22select -assert-count 1 t:LUT3 23select -assert-count 3 t:inpad 24select -assert-count 1 t:outpad 25 26select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D 27 28 29design -load read 30hierarchy -top latchsr 31proc 32# Can't run any sort of equivalence check because latches are blown to LUTs 33synth_quicklogic 34cd latchsr # Constrain all select calls below inside the top module 35select -assert-count 1 t:LUT2 36select -assert-count 1 t:LUT4 37select -assert-count 5 t:inpad 38select -assert-count 1 t:outpad 39 40select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D 41