1 2// test taken from systemcaes from iwls2005 3 4module subbytes_00(clk, reset, start_i, decrypt_i, data_i, ready_o, data_o, sbox_data_o, sbox_data_i, sbox_decrypt_o); 5 6input clk; 7input reset; 8input start_i; 9input decrypt_i; 10input [31:0] data_i; 11output ready_o; 12output [31:0] data_o; 13output [7:0] sbox_data_o; 14input [7:0] sbox_data_i; 15output sbox_decrypt_o; 16 17reg ready_o; 18reg [31:0] data_o; 19reg [7:0] sbox_data_o; 20reg sbox_decrypt_o; 21 22reg [1:0] state; 23reg [1:0] next_state; 24reg [31:0] data_reg; 25reg [31:0] next_data_reg; 26reg next_ready_o; 27 28always @(posedge clk or negedge reset) 29begin 30 if (!reset) begin 31 data_reg = 0; 32 state = 0; 33 ready_o = 0; 34 end else begin 35 data_reg = next_data_reg; 36 state = next_state; 37 ready_o = next_ready_o; 38 end 39end 40 41reg [31:0] data_i_var, data_reg_128; 42reg [7:0] data_array [3:0]; 43reg [7:0] data_reg_var [3:0]; 44 45always @(decrypt_i or start_i or state or data_i or sbox_data_i or data_reg) 46begin 47 data_i_var = data_i; 48 49 data_array[0] = data_i_var[ 31: 24]; 50 data_array[1] = data_i_var[ 23: 16]; 51 data_array[2] = data_i_var[ 15: 8]; 52 data_array[3] = data_i_var[ 7: 0]; 53 54 data_reg_var[0] = data_reg[ 31: 24]; 55 data_reg_var[1] = data_reg[ 23: 16]; 56 data_reg_var[2] = data_reg[ 15: 8]; 57 data_reg_var[3] = data_reg[ 7: 0]; 58 59 sbox_decrypt_o = decrypt_i; 60 sbox_data_o = data_array[state]; 61 next_state = state; 62 next_data_reg = data_reg; 63 64 next_ready_o = 0; 65 data_o = data_reg; 66 67 if (state) begin 68 if (start_i) begin 69 next_state = 1; 70 end 71 end else begin 72 data_reg_var[state] = sbox_data_i; 73 data_reg_128[ 31: 24] = data_reg_var[0]; 74 data_reg_128[ 23: 16] = data_reg_var[1]; 75 data_reg_128[ 15: 8] = data_reg_var[2]; 76 data_reg_128[ 7: 0] = data_reg_var[3]; 77 next_data_reg = data_reg_128; 78 next_state = state + 1; 79 end 80end 81 82endmodule 83