xref: /dports/cad/yosys/yosys-yosys-0.12/tests/various/design1.ys

read_verilog <<EOT
module top(input i, output o);
assign o = i;
endmodule
EOT
design -stash foo
design -delete foo
logger -expect error "No saved design 'foo' found!" 1
design -delete foo